Interconnect structure with improved conductive properties and associated systems and methods

ABSTRACT

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. application Ser. No.15/229,618 filed Aug. 5, 2016, which is a divisional of U.S. patentapplication Ser. No. 14/281,449, filed May 19, 2014, now U.S. Pat. No.9,412,675, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The disclosed embodiments relate to interconnect structures insemiconductor die assemblies. In several embodiments, the presenttechnology relates to an interconnect structure with improved conductiveproperties, including improved electrical and/or thermal properties.

BACKGROUND

Packaged semiconductor dies, including memory chips, microprocessorchips, and imager chips, typically include a semiconductor die mountedon a substrate and encased in a plastic protective covering. The dieincludes functional features, such as memory cells, processor circuits,and imager devices, as well as bond pads electrically connected to thefunctional features. The bond pads can be electrically connected toterminals outside the protective covering to allow the die to beconnected to higher level circuitry. Within some packages, semiconductordies can be stacked upon and electrically connected to one another byindividual interconnects placed between adjacent dies.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor die assemblyconfigured in accordance with an embodiment of the present technology.

FIG. 2 is an enlarged cross-sectional view of a semiconductor devicethat includes interconnect structures configured in accordance with anembodiment of the present technology.

FIGS. 3A-3I are cross-sectional views illustrating a semiconductordevice at various stages in a method for making interconnect structuresor other connectors in accordance with selected embodiments of thepresent technology.

FIG. 4 is a schematic view of a system that includes a semiconductor dieassembly configured in accordance with embodiments of the presenttechnology.

DETAILED DESCRIPTION

Specific details of several embodiments of stacked semiconductor dieassemblies with improved thermal performance and associated systems andmethods are described below. The terms “semiconductor device” and“semiconductor die” generally refer to a solid-state device thatincludes semiconductor material, such as a logic device, memory device,or other semiconductor circuit, component, etc. Also, the terms“semiconductor device” and “semiconductor die” can refer to a finisheddevice or to an assembly or other structure at various stages ofprocessing before becoming a finished device. Depending upon the contextin which it is used, the term “substrate” can refer to a wafer-levelsubstrate or to a singulated, die-level substrate. A person skilled inthe relevant art will recognize that suitable steps of the methodsdescribed herein can be performed at the wafer level or at the dielevel. Furthermore, unless the context indicates otherwise, structuresdisclosed herein can be formed using conventionalsemiconductor-manufacturing techniques. Materials can be deposited, forexample, using chemical vapor deposition, physical vapor deposition,atomic layer deposition, spin coating, and/or other suitable techniques.Similarly, materials can be removed, for example, using plasma etching,wet etching, chemical-mechanical planarization, or other suitabletechniques. A person skilled in the relevant art will also understandthat the technology may have additional embodiments, and that thetechnology may be practiced without several of the details of theembodiments described below with reference to FIGS. 1-4.

As used herein, the terms “vertical,” “lateral,” “upper” and “lower” canrefer to relative directions or positions of features in thesemiconductor die assemblies in view of the orientation shown in theFigures. For example, “upper” or “uppermost” can refer to a featurepositioned closer to the top of a page than another feature. Theseterms, however, should be construed broadly to include semiconductordevices having other orientations.

FIG. 1 is a cross-sectional view of a semiconductor die assembly 100(“assembly 100”) configured in accordance with an embodiment of thepresent technology. The assembly 100 includes a stack of firstsemiconductor dies 102 a carried by a second semiconductor die 102 b(collectively “semiconductor dies 102”). The second semiconductor die102 b, in turn, is carried by an interposer 120. The interposer 120 caninclude, for example, a semiconductor die, a dielectric spacer, and/oranother suitable substrate having electrical connectors (not shown),such as vias, metal traces, etc.) connected between the interposer 120and a package substrate 125. The package substrate 125 can include, forexample, an interposer, a printed circuit board, another logic die, oranother suitable substrate connected to package contacts 127 (e.g., bondpads) and electrical connectors 128 (e.g., solder balls) thatelectrically couple the assembly 100 to external circuitry (not shown).In some embodiments, the package substrate 125 and/or the interposer 120can be configured differently. For example, in some embodiments theinterposer 120 can be omitted and the second semiconductor die 102 b canbe directly connected to the package substrate 125.

The assembly 100 can further include a thermally conductive casing 110(“casing 110”). The casing 110 can include a cap portion 112 and a wallportion 113 attached to or integrally formed with the cap portion 112.The cap portion 112 can be attached to the top-most first semiconductordie 102 a by a first bond material 114 a (e.g., an adhesive). The wallportion 113 can extend vertically away from the cap portion 112 and beattached to a peripheral portion 106 of the first semiconductor die 102a (known to those skilled in the art as a “porch” or “shelf) by a secondbond material 114 b (e.g., an adhesive). In addition to providing aprotective covering, the casing 110 can serve as a heat spreader toabsorb and dissipate thermal energy away from the semiconductor dies102. The casing 110 can accordingly be made from a thermally conductivematerial, such as nickel (Ni), copper (Cu), aluminum (Al), ceramicmaterials with high thermal conductivities (e.g., aluminum nitride),and/or other suitable thermally conductive materials.

In some embodiments, the first bond material 114 a and/or the secondbond material 114 b can be made from what are known in the art as“thermal bond materials” or “TIMs”, which are designed to increase thethermal contact conductance at surface junctions (e.g., between a diesurface and a heat spreader). TIMs can include silicone-based greases,gels, or adhesives that are doped with conductive materials (e.g.,carbon nano-tubes, solder materials, diamond-like carbon (DLC), etc.),as well as phase-change materials. In other embodiments, the first bondmaterial 114 a and/or the second bond material 114 b can include othersuitable materials, such as metals (e.g., copper) and/or other suitablethermally conductive materials.

Some or all of the first and/or second semiconductor dies 102 can be atleast partially encapsulated in a dielectric underfill material 116. Theunderfill material 116 can be deposited or otherwise formed aroundand/or between some or all of the dies to enhance a mechanicalconnection with a die and/or to provide electrical isolation betweenconductive features and/or structures (e.g., interconnects). Theunderfill material 116 can be a non-conductive epoxy paste, a capillaryunderfill, a non-conductive film, a molded underfill, and/or includeother suitable electrically-insulative materials. In severalembodiments, the underfill material 116 can be selected based on itsthermal conductivity to enhance heat dissipation through the dies of theassembly 100. In some embodiments, the underfill material 116 can beused in lieu the first bond material 114 a and/or the second bondmaterial 114 b to attach the casing 110 to the top-most firstsemiconductor die 102 a

The semiconductor dies 102 can each be formed from a semiconductorsubstrate, such as silicon, silicon-on-insulator, compound semiconductor(e.g., Gallium Nitride), or other suitable substrate. The semiconductorsubstrate can be cut or singulated into semiconductor dies having any ofvariety of integrate circuit components or functional features, such asdynamic random-access memory (DRAM), static random-access memory (SRAM),flash memory, other forms of integrated circuit devices, includingmemory, processing circuits, imaging components, and/or othersemiconductor devices. In selected embodiments, the assembly 100 can beconfigured as a hybrid memory cube (HMC) in which the firstsemiconductor dies 102 a provide data storage (e.g., DRAM dies) and thesecond semiconductor die 102 b provides memory control (e.g., DRAMcontrol) within the HMC. In some embodiments, the assembly 100 caninclude other semiconductor dies in addition to and/or in lieu of one ormore of the semiconductor dies 102. For example, such semiconductor diescan include integrated circuit components other than data storage and/ormemory control components. Further, although the assembly 100 includesnine dies stacked on the interposer 120, in other embodiments theassembly 100 can include fewer than nine dies (e.g., six dies) or morethan nine dies (e.g., twelve dies, fourteen dies, sixteen dies,thirty-two dies, etc.). For example, in one embodiment, the assembly 100can include four memory dies stacked on two logic dies. Also, in variousembodiments, the semiconductor dies 102 can have different sizes. Forexample, in some embodiments the second die 102 b can have the samefootprint as at least one of the first semiconductor dies 102 a.

As further shown in FIG. 1, the assembly 100 includes a plurality ofinterconnect structures 130 positioned between each of the semiconductordies 102. At least a portion of the interconnect structures 130 can becoupled to a redistribution network 147 having conductive traces 140 orother suitable conductive structures (e.g., contact pads) formed on eachof the semiconductor dies 102. The conductive traces 140 traces, inturn, can be coupled to a plurality of through-substrate interconnects(TSVs) 142. The TSVs 142 can extend through each of the semiconductordies 102 and couple together corresponding conductive traces 140 onopposite sides of each of the dies 102. In the illustrated embodiment,the TSVs 142 are disposed toward the center of the semiconductor dies102, and the conductive traces 140 fan outwardly from the TSVs 142 toconnect to individual interconnect structures 130. In other embodiments,however, the TSVs 142, the conductive traces 140, and/or theinterconnect structures 130 can be arranged differently. Further, inseveral embodiments the redistribution network 147 can be omitted andthe interconnect structures 130 can be in direct contact with thecorresponding TSVs 142.

The interconnect structures 130 can each include a first conductivemember 132 and a second conductive member 133 coupled to the firstconductive member 132 by a bond material 135. In one aspect of theembodiment of FIG. 1, the bond material 135 can at least partiallyencapsulate the second conductive member 133 within a depression 137located in the first conductive member 132. As described in greaterdetail below, in several embodiments the bond material 135 can beconfigured to enhance the electrical and/or thermal coupling between thefirst and second conductive members 132 and 133.

In some embodiments, certain interconnect structures 130 can be “dummy”structures that are not electrically coupled to any of the semiconductordies 102. For example, in the illustrated embodiment, the outermostinterconnect structures 130 at each of the semiconductor dies 102 arenot connected to the redistribution network 147. In several embodiments,these “dummy” interconnect structures can be positioned at variouslocations on the semiconductor dies 102 (e.g., toward the periphery,center, etc.) to provide additional mechanical support and/or enhanceheat transfer throughout the regions between the semiconductor dies 102.

FIG. 2 is an enlarged view of a semiconductor device 205 that includesindividual interconnect structures 230 configured in accordance with anembodiment of the present technology. As shown, each of the interconnectstructures 230 includes a first conductive member, or cup 232, coupledto a second conductive member, or pillar 233, by a bond material 235.The cup 232 is attached to a first substrate 204 a (e.g., asemiconductor wafer or die) and can include a recessed surface 231defining a depression 237 that contains the bond material 235. In theillustrated embodiment, the cup 232 extends (e.g., projects) beyond asurface of the first substrate 204 a. In other embodiments, however, thecup 232 can be at least partially recessed below this surface. Thepillar 233 is attached to a second substrate 204 b (e.g., asemiconductor wafer or die) and extends (e.g., projects) at leastpartially into the depression 237 of the cup 232. In severalembodiments, the cup 232 and the pillar 233 can each include copper orcopper alloy materials. Further, in some embodiments, a first barriermaterial 274 (e.g., a nickel material) can be formed on the cup 232, anda second barrier material 284 (e.g., a nickel material) can be formed onthe pillar 233.

In the illustrated embodiment, the bond material 235 forms a conductivejoint 236 that at least partially encapsulates the pillar 233 within thecup 232. The bond material can include, for example, solder (e.g., metalsolder) and/or other suitable conductive bonding materials (e.g., aconductive epoxy or paste). The bond material 235 can be heated (e.g.,reflowed) and react with the conductive materials of the cup 232 and thepillar 233 to form intermetallics 234 (identified individually as firstand second intermetallics 234 a and 234 b) that bond the bond material235 to the cup 232 and the pillar 233. For example, when a tin/silver(SnAg) bond material reacts with a nickel-based barrier material, thereaction can form tin/nickel (SnNi) intermetallics. In some embodiments,the bond material 235 can form a third intermetallic 234 c when the bondmaterial 235 reacts with the conductive material (e.g., copper) at asidewall 238 of the pillar 332. For example, the reaction of tin/silversolder with copper can form a tin/copper intermetallic (SnCu).

In contrast to the interconnect structures 230, conventional metalcontacts typically have flat contact surfaces that are bonded togetherwith metal solder. For example, metal contacts can be bonded together byplacing a solder ball between the metal contacts and then reflowing thesolder so that it reacts with the metal at the contact surfaces of thecontacts. One challenge with conventional solder joints, however, isthat solder can migrate or spread during reflow. For example, the soldercan be displaced when it squeezed between the metal contacts. Also,certain forces, such as surface tension, can cause the solder to wickaway from a contact surface and onto other surfaces. One specificchallenge occurs when the solder wicks onto and forms an intermetallicon the sidewalls of a metal contact. This intermetallic at the sidewallscan ultimately degrade the overall electrical and/or thermalconductively of the contact. For example, conventional tin/copperintermetallics can reduce the overall thermal conductivity of acopper-based contact. Further, in vertical interconnects (e.g., copperposts), the solder can consume a substantial amount of metal, which cancause the interconnect to slump and/or form voids in the sidewalls(e.g., due to Kirkendall voiding).

Interconnect structures configured in accordance with severalembodiments of the present technology, can address these and otherlimitations of conventional interconnects and related structures. Inparticular, the cup 232 and the pillar 233 can be configured to preventthe formation of intermetallics outside of the depression 237. In oneaspect of this embodiment, the cup 232 can contain the bond materialwithin the depression 237 during reflow to prevent the spread ormigration of the bond material 235. Also, in some embodiments, surfacetension can hold the bond material 235 within the depression 237. Inanother aspect of this embodiment, the volume of the bond material 235can be selected to limit the conversion of conductive materials (e.g.,copper) into intermetallics. For example, the volume can be selectedsuch that the bond material 235 is fully consumed before a substantialportion or any of the material at the sidewall 238 of the pillar 233 isconverted into an intermetallic. In several embodiments the bondmaterial 235 can be fully converted into intermetallics. In suchembodiments, the first intermetallic 234 a can contact the secondintermetallic 234 b and/or the third intermetallic 234 c within thedepression 237.

FIGS. 3A-3I are partially schematic cross-sectional views illustrating aportion of a semiconductor device 305 at various stages in a method formaking interconnect structures in accordance with selected embodimentsof the present technology. Referring first to FIG. 3A, the semiconductordevice 305 includes a first substrate 304 a (e.g., a silicon wafer ordie) and a dielectric material 350 a (e.g., silicon oxide) formedthereon. The semiconductor device 305 further includes a conductivetrace 340 a and a contact pad 343 a buried within the dielectricmaterial 350 a. As shown, the conductive trace 340 a is coupled to asubstrate contact 307 (e.g., a copper bond pad), and the contact pad 343a is electrically isolated from the substrate contact 307 by thedielectric material 350 a. In several embodiments, the conductive trace340 a and the contact pad 343 a can each include copper, copper alloy,and/or other suitable conductive materials.

FIG. 3B shows the semiconductor device 305 after forming a mask 360(e.g., a photoresist mask, hard mask, etc.) and openings 352 in thedielectric material 350 a. The openings 352 can be formed by removing(e.g., etching) portions of the dielectric material 350 a throughcorresponding mask openings 361 defined in the mask 360. As shown inFIG. 3B, the openings 352 in the dielectric material 350 a can exposeportions of the underlying conductive trace 340 a and the contact pad343 a.

FIG. 3C shows the semiconductor device 305 after forming conductivemembers, or pillars 333, on the conductive trace 340 a and the contactpad 343 a. In several embodiments, the pillars 333 can be formed bydepositing a seed material 372 (e.g., copper) on sidewalls 362 of themask openings 361 (FIG. 3B) and electroplating a conductive material 370(e.g., copper) onto the conductive trace 340 a and the contact pad 343a. In the illustrated embodiment, a barrier material 374 (e.g., nickel)and an interface material 375 (e.g., palladium) can also beelectroplated in sequence onto the conductive material 372. In otherembodiments, the pillars 333 can be formed by other suitable depositiontechniques, such as sputter deposition.

FIG. 3D shows the semiconductor device 305 after forming an opening 308in the first substrate 304 a and forming a protective material 363 overthe pillars 333. As shown, the opening 308 extends through the firstsubstrate 304 a and exposes a portion of the substrate contact 307toward the base of the opening 308. In several embodiments, the opening308 can be formed by first thinning the first substrate 304 a (e.g., viaetching, backgrinding, etc.) and then removing substrate material (e.g.,via an etch). In the illustrated embodiment, the protective material orfilm 363 (e.g., a polymeric film) can protect the pillars 333 duringmanufacturing.

FIG. 3E shows the semiconductor device 305 after forming a TSV 342, adielectric material 350 b, a conductive trace 340 b, and a contact pad343 b. The TSV 342 can be formed by filling the opening 308 (FIG. 3D) inthe first substrate 304 a with a conductive material 376, such as copperor copper alloy. The dielectric material 350 b can include openings 353that expose portions of the underlying conductive trace 340 b and thecontact pad 343 b. In several embodiments, the conductive trace 340 b,the contact pad 343 b, and the dielectric material 350 b can be similarin structure and function as the conductive trace 340 a, the contact pad343 a, and the dielectric material 350 a.

FIG. 3F shows the semiconductor device 305 after forming a mask 365 onthe dielectric material 350 b. The mask 365 include mask openings 366having a seed material (e.g., a copper seed material) formed onsidewalls 367 of the mask 365 within the mask openings 366. In theillustrated embodiment, the mask openings 366 are configured to exposeedge portions 355 of the dielectric material 350 b toward the base ofthe openings 353.

FIG. 3G shows the semiconductor device 305 after forming conductivemembers, or cups 332, within the mask openings 366 (FIG. 3F) of the mask365. In several embodiments, the cups 332 can be formed byelectroplating a conductive material 378 (e.g., copper) onto theconductive trace 340 b, the contact pad 343 b, and the seed material377. As further shown in FIG. 3G, the cups 332 each include a recessedsurface 331 defining a depression 337. It is believed that the edgeportions 355 of the dielectric material 350 b can be configured suchthat the depression 337 is formed in-situ during electroplating. Inparticular, it is believed that the edge portions 355 can influence thephysical and/or chemical interactions that occur during electroplatingtoward the sidewalls 367 of the mask 365. These chemical and/or physicalinteractions are believed to cause non-uniform metal deposition thatresult in the formation of the depression 337. For example, it isbelieved that the edge portions 355 may create discontinuities in thecomposition of the seed material 377, produce localized regions of highcurrent density in the electroplating current, and/or cause non-lineardiffusion of metal ions. Without wishing to be bound by theory, it isbelieved that a width W₁ of the peripheral portion in the range of about5 μm to about 20 μm (e.g., 10 μm) can result in the formation of thedepression 337. Further, without wishing to be bound by theory, it isbelieved that the size (e.g., the depth) of the depression 337 can becorrelative with the size (e.g., the lateral width) of the edge portions355.

In other embodiments, the depression 337 can be formed using additionalor alternate techniques. For example, in some embodiments the anelectroplating bath can include certain additives, such as organicadditives (e.g., brighteners, levers, surfactants, etc.), that causesmetal to deposit preferentially toward the sidewalls 367 of the mask365. In some embodiments, the conductive material 378 can be etched toform the depression 337 rather than employing the edge portions 355alone or at all. Further, while having a generally curved profile in theillustrated embodiment, in other embodiments the depression 337 can havea different shape, size, depth, and/or profile (e.g., a rectangularprofile).

FIG. 3H shows the semiconductor device 305 after forming a barriermaterial 384 (e.g., nickel), an interface material 385 (e.g.,palladium), and a bond material 335 (e.g., tin/silver) at leastpartially within the depression 337. In several embodiments, the barriermaterial 384, the interface material 385, and the bond material 335 canbe electroplated in sequence onto the conductive material 378 of thecups 332. In another embodiment, one or more of these materials can beformed by other deposition techniques. For example, in certainembodiments, the bond material 335 can be disposed in the form of asolder ball positioned on the interface material 385 within thedepression 337.

FIG. 3I shows the semiconductor device 305 after removing the mask 365and the protective film 363 (FIG. 3H) and coupling the pillars 333 ofthe first substrate 304 a to corresponding cups 332 of a secondsubstrate 304 b. In several embodiments, the cups 332 of the secondsubstrate 304 b can be generally similar in structure and function tothe cups 332 of the first substrate 304 a (FIG. 3H). As shown, the bondmaterial 335 has been heated (e.g., reflowed) and the pillars 333 havebeen inserted into the corresponding depression 337 of each of the cups332. In some embodiments, the volume of the bond material 335 can beselected to account for displacement of the bond material 335 due to theinsertion of the pillars 333 into the cups 332. Once the pillars 333 areinserted into position, the bond material 335 can be allowed to cool andsolidify into a conductive joint 336 between each pair of the pillar andcups 332 and 333.

Any one of the interconnect structures and/or semiconductor dieassemblies described above with reference to FIGS. 1-3I can beincorporated into any of a myriad of larger and/or more complex systems,a representative example of which is system 490 shown schematically inFIG. 4. The system 490 can include a semiconductor die assembly 400, apower source 492, a driver 494, a processor 496, and/or other subsystemsor components 498. The semiconductor die assembly 400 can includefeatures generally similar to those of the stacked semiconductor dieassemblies described above, and can therefore include various featuresthat enhance heat dissipation. The resulting system 490 can perform anyof a wide variety of functions, such as memory storage, data processing,and/or other suitable functions. Accordingly, representative systems 490can include, without limitation, hand-held devices (e.g., mobile phones,tablets, digital readers, and digital audio players), computers, andappliances. Components of the system 490 may be housed in a single unitor distributed over multiple, interconnected units (e.g., through acommunications network). The components of the system 490 can alsoinclude remote devices and any of a wide variety of computer readablemedia.

From the foregoing, it will be appreciated that specific embodiments ofthe technology have been described herein for purposes of illustration,but that various modifications may be made without deviating from thedisclosure. For example, although several of the embodiments of thesemiconductor dies assemblies are described with respect to HMCs, inother embodiments the semiconductor die assemblies can be configured asother memory devices or other types of stacked die assemblies. Inaddition, while in the illustrated embodiments certain features orcomponents have been shown as having certain arrangements orconfigurations, other arrangements and configurations are possible. Forexample, while the TSV 342 (FIG. 3E) in the illustrated embodiment isformed after front-end metallization (i.e., after forming the substratecontact 307), in other embodiments the TSV 342 can be formed before orconcurrently with front-end metallization. Moreover, although advantagesassociated with certain embodiments of the new technology have beendescribed in the context of those embodiments, other embodiments mayalso exhibit such advantages and not all embodiments need necessarilyexhibit such advantages to fall within the scope of the technology.Accordingly, the disclosure and associated technology can encompassother embodiments not expressly shown or described herein.

I/We claim:
 1. A method of forming a semiconductor die assembly, themethod comprising: inserting at least a portion of a first conductivemember on a first semiconductor die into at least a portion of adepression of a second conductive member on a second semiconductor die,wherein the second semiconductor die includes a dielectric material anda conductive trace, wherein the dielectric material includes an openingthat (a) extends at least partially through the dielectric material, and(b) exposes a portion of the conductive trace, and wherein the secondconductive member projects outwardly from the exposed portion of theconductive trace; and at least partially filling the depression of thesecond conductive member with a bonding material.
 2. The method of claim1 wherein the portion of the first conductive member is a first portion,the method further comprising: reacting the bond material with a secondportion of the first conductive member to form a first intermetallic atleast partially within the depression of the second conductive member;and reacting the bond material with a portion of the second conductivemember to form a second intermetallic at least partially within thedepression of the second conductive member.
 3. The method of claim 2wherein the first and second intermetallics each include tin/nickel(SnNi) or tin/copper (SnCu), and wherein the bond material includestin/silver (SnAg).
 4. The method of claim 1, further comprising forminga redistribution network on the first semiconductor die, wherein thefirst semiconductor die includes a plurality of through-substrate vias(TSVs) electrically coupled to the redistribution network.
 5. The methodof claim 1 wherein the second conductive member includes verticallystraight sidewalls.
 6. The method of claim 1 wherein the secondconductive member is generally aligned with the depression of the secondconductive member.
 7. The method of claim 1 wherein the bond material inthe depression covers the portion of the first conductive member.
 8. Amethod of forming a semiconductor device, the method comprising: forminga semiconductor die including a dielectric material having an opening,and conductive feature at least partially exposed through the opening;depositing a bond material within a depression located in a firstconductive member, wherein the first conductive member projects from theconductive feature and extends beyond the dielectric material, andwherein the first conductive member is generally aligned with theopening of the dielectric material; and inserting at least a portion ofa second conductive member into the bond material such that the bondmaterial covers the portion of the second conductive member.
 9. Themethod of claim 8, further comprising heating the bond material to formintermetallics with the depression located in the first conductivemember.
 10. The method of claim 8 wherein the bond material includesmetal solder.
 11. The method of claim 8 wherein the semiconductor die isa first semiconductor die, the dielectric material is a first dielectricmaterial, the opening is a first opening, and the conductive feature isa first conductive feature, the method further comprising: forming asecond semiconductor die including a second dielectric material having asecond opening, and a second conductive feature at least partiallyexposed through the opening; and forming the second conductive member bydepositing a conductive material in the second opening on the secondconductive feature.
 12. A method of forming an interconnect structure,the method comprising: disposing a bond material within a depressionlocated in a first conductive member; and inserting at least a portionof a second conductive member into the bond material such that anoutermost surface of the second conductive member is covered by the bondmaterial, wherein the second conductive member— extends outwardly from aconductive trace of a semiconductor die, and includes generally verticalsidewalls.
 13. The method of claim 12, further comprising heating thebond material to fully convert the bond material into one or moreintermetallics.
 14. The method of claim 12 wherein the bond materialincludes solder, and wherein the method further includes reflowing thesolder.
 15. The method of claim 12, further comprising: reacting thebond material with a portion of the first conductive member to form afirst intermetallic at least partially within the depression; andreacting the bond material with a portion of the second conductivemember to form a second intermetallic at least partially within thedepression.
 16. The method of claim 15 wherein the first intermetallicand the second intermetallic each includes tin/nickel (SnNi).
 17. Themethod of claim 15 wherein the first intermetallic includes tin/nickel(SnNi) and the second intermetallic includes tin/copper (SnCu).